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The following page gives a rough overview about several interfaces which are often used in ASICs, in terms of employment, signal specification, possible data rates and other characteristics. Thus of course the descriptions do not hold the complete set of parameters of the concerning interfaces.

ACPI Advanced Configuration Power Interface
AMBA Advanced Microcontroller Bus Architecture
DVB Digital Video Broadcast
ESCON Enterprice System Connection
FireWire, IEEE 1394
GMII Gigabit Media Independent Interface
GPSI General Purpose Serial Interface
HIPPI High Performance Parallel Interface
HomePNA Home Phoneline Networkin
HPI Host Processor Interface
HSSI High-Speed Serial Interface
I2C Inter-IC
IrDA Infrared Data Association
LA-1A/B Look Aside Interface
MDIO Management Data I/O
MII Media independent Interface
PCI / PCI-X / PCI-Express Peripheral Component Interconnect ( -X / Express)
PC Parallel Port
POS Packet over SONET/SDH
PCMCIA Personal Computer Memory Card International Association
RapidIO / Serial RapidIO
RGMII Reduced Gigabit Media Independent Interface
RMII Reduced Media Independent Interface
RS232   RS-422 and RS-423   RS-485 Serial Interfaces
SCSI Small Computer System Interface
SERDES Serial/Desirial
SPI / SFI System Packet Interface (SPI) and the SERDES Framer Interface
SDH Synchronous Digital Hierarchy
SONET Synchronous Optical Network
USB / USB On-The-Go Universal Serial Bus
UTOPIA Universal Test & Operations PHY Interface for ATM
V.24, V.35, V.42, V.110, V.120, V.FAST
VL-Bus Vesa Local Bus


ACPI Advanced Configuration Power Interface
A foundation technology and industry initiative that enables the operating system to intelligently control the amount of power used by each device attached to the computer. Generally specifies power management for motherboard devices and the BIOS.

AMBA Advanced Microcontroller Bus Architecture
This specification from ARM (Advanced RISC Machines) defines an on-chip communications standard for designing high-performance embedded microcontrollers. Three distinct buses are defined within the AMBA specification

  • AHB (Advanced High-speed Bus) is for high-performance, high clock frequency system modules. The AHB acts as the high-performance system backbone bus and supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low power peripheral macrocell functions. AMBA AHB implements the features required for high-performance, high-clock frequency systems.
  • APB Advanced Peripheral Bus is ideal for ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, I/O ports, etc. Connection to the main system bus is via a system-to-peripheral bus, bridge. APB has been updated in the new AMBA Rev 2.0 Specification to align with current synthesis design flows. The APB bus is characterised by
    • - A simple bus Unpipelined architecture
      - Easy to implement with all the peripherals acting as slaves
      - Low gate count
      - Low power
      - Reduced loading of the main system bus by isolating peripherals behind the bridge
      - Peripheral bus signals only active during low bandwidth peripheral transfers.

DVB  Digital Video Broadcasting
European version of U.S. ATV. Commonly used in satellite transmission systems.

  • DVB-ASI  DVB-Asynchronous Serial Interface
    Digital Video Broadcast-Asynchronous Serial Interface. The DVB standards board promotes the ASI design as an industry-standard way to connect components such as encoders, modulators, receivers, and multiplexers. The maximum defined data rate on such a link is 270 Mbps, with useful payload variable ­ depending upon equipment manufacturer. This is an MPEG-2 transport.
  • DVB-SDI  DVB-Serial Digital Interface
    SMPTE 259M (1986). Serial Digital Interface. A serial digital video data stream consisting of video plus four audio channels making up a 270 Mbps transmission, or 360 Mbps for wide-screen (16:9 SDTV).
  • DVB-SDTI DVB-Serial Digital Transport Interface
    SMPTE 305M (1998). Uses SMPTE 259 (DVB-SDI) as a carrier for other information. User payload is approximately 225 Mbps (using active line transport).
  • DVB-SPI DVB-Synchronous Parallel Interface
  • DVB-SSI DVB-Synchronous Serial Interface

ESCON  Enterprice System Connection
This interface type interface is a subset of the ESA/390 architecture and has been announced be IBM and describes the data transfer and information exchange for serial optical connections at 200 Mbps. ESCON connects main frames to each other and main frames with peripheral units. A network can be set up to a distance of 60 km, which allows dynamical switching of all type of point to point connections. The data transfer is done via a fibre cable using 2 fibres with a maximum transfer rate of 200 Mbit/s. Transmitting is done with LED for distances up to 3 km, with laser for distances up to 60 km. Basis for data transfer between 2 devices is a point to point connection.
The ESCON technology offers a connection for all input/ output devices and channel to channel adapters. A connection can be done either direct or by using the ESCON director unit. Major benefits will be achieved by using the ESCON directors which is a central element, which connects any channel with any channel or peripheral unit in a point to point connection.
This technology needs for all possible connections a commen ESCON interface. The connections are directional symetrical. This allows an easy design for channel to channel connections. Instead of using an additional adapter the ESCON hardware can be used by only a change in the micro programm to perform the channel to channel functions.
The ESCON technology allows dynamical connections, which are easy to install or exstall, controlled by a protocoll set in the architecture. Due to the fact, that only active point to point connections are switched during data transfer, all inactive connections are free for other operations. This flexibility can be used totally, because the ESCON director is switching all connections at the same time in parallel. Due to the star connection a defective part has only influence to the direct connected unit. All other connections remain working and the failing part can easily be replaced without desturbing other connections.

FireWire, IEEE 1394
A very fast external bus standard that supports data transfer rates of up to 400 Mbps (400 million bits per second). Products supporting the IEEE 1394 standard go under different names, depending on the company. Apple, which originally developed the technology, uses the trademarked name FireWire. Other companies use other names, such as and Lynx, to describe their IEEE 1394 products. A single IEEE 1394 port can be used to connect up 63 external devices. In addition to its high speed, this interface also supports isochronous data delivering data at a guaranteed rate. This makes it ideal for devices that need to transfer high levels of data in real-time, such as video devices. Although extremely fast and flexible, IEEE 1394 is also expensive. Like USB, IEEE 1394 supports both Plug-and-Play and hot plugging, and also provides power to peripheral devices.
The IEEE 1394 standard defines both a backplane physical layer and a point-to-point cable-connected virtual bus implementations. The backplane version operates at 12.5, 25 or 50 Mbits/sec. The cable version supports data rates of 100, 200 and 400 Mbits/ sec. Both versions are compatible at the link layer and above. The Standard defines the media, topology and the protocol.

GMII Gigabit Media Independent Interface
An IEEE 802.3z standard 10 bit interface to external transceivers (MAC Interface). GMII can be used for Gigabit Ethernet.  (see also RGMII, MII and RMII)

GPSI General Purpose Serial Interface
Allows direct access to/from a MAC in the applications of MII interface. Seven signals which comprise the GPSI are TX_CLK, TX_EN, TX_DATA, RX_CLK, RX_DATA, CRS, and CLSN. Of these TX_EN and TX_DATA are in the one direction, the other five are in the opposite direction.
The transmit clock, TX_CLK, provides the timing reference for the transfer of TX_EN and TX_DATA signals from the MAC to the 78Q2131. TX_DATA is captured on the rising edge of TX_CLK when TX_EN is asserted.

HIPPI  High Performance Parallel Interface
Standard technology for physically connecting chips at short distances and high speeds. HIPPI transfers 32 bits in parallel at a data transfer rate of 0.8 Gbps. Wide HIPPI transfers 64 bits at a time to yield 1.6 Gbps. New HIPPI standards supporting rates of 6.4 Gbps are under development. This standard became an official ANSI standard in 1990 and is used primarily to connect supercomputers and to provide high-speed backbones for local-area networks.

HomePNA Home Phoneline Networking

HPI Host Processor Interface
The Host Processor Interface is an asynchronous 8-bit parallel interface, compatible with both Motorola and Intel microprocessor busses and supports word (16-bit) transfers. The maximum transfer rate for the HPI is half of the processor clock frequency.

HSSI High-Speed Serial Interface
A a DTE/DCE interface that was developed by Cisco Systems and T3plus Networking to address the need for high-speed communication over WAN links. HSSI defines both electrical and physical interfaces on DTE and DCE devices. It operates at the  physical layer of the OSI reference model.

      Maximum signaling rate: 52 Mbps
      Maximum cable length: 50 feet
      Number of connector points: 50
      Interface: DTE-DCE
      Electrical technology: Differential ECL
      Typical power consumption: 610 mW
      Topology: Point-to-point
      Cable type: Shielded twisted-pair wire

The maximum signaling rate of HSSI is 52 Mbps. At this rate, HSSI can handle the T3 speeds (45 Mbps) of many of today's fast WAN technologies, as well as the Office Channel-1 (OC-1) speeds (52 Mbps) of the synchronous digital hierarchy (SDH). In addition, HSSI easily can provide high-speed connectivity between LANs, such as Token Ring and Ethernet.
The use of differential emitter-coupled logic (ECL) helps HSSI achieve high data rates and low noise levels. ECL has been used in Cray computer system interfaces for years and is specified by the ANSI High-Performance Parallel Interface (HIPPI) communications standard for supercomputer LAN communications. ECL is an off-the-shelf technology that permits excellent retiming on the receiver, resulting in reliable timing margins. HSSI uses a subminiature, FCC-approved 50-pin connector that is smaller than its V.35 counterpart. To reduce the need for male-male and female-female adapters, HSSI cable connectors are specified as male. The HSSI cable uses the same number of pins and wires as the Small Computer Systems Interface 2 (SCSI-2) cable, but the HSSI electrical specification is more concise.

HyperTransport technology is a new high-speed, high-performance, point-to-point link for integrated circuits for new generation host system interconnect. It provides the absolute lowest latency method of communicating with processors. It provides a universal connection that is designed by the 'HyperTransport Technology Consortium' to reduce the number of buses within a system, provide a link for embedded applications, and enable highly scalable multiprocessing systems. It was developed to enable the chips inside of PCs, networking and communications devices to communicate with each other up to 48 times faster than other currently used technologies. The Bandwidth in each direction is 100 MB/s to 11.2 GB/s. Data throughput is up to 22.4 GB/s). Formerly named as Lightning Data Transport (LDT), HyperTransport is a packet-based link implemented on two unidirectional sets of signals and connects two devices. The HyperTransport link uses scalable frequency and data width to achieve scalable bandwidth.
HyperTransport connection consist of the signals CLK (1, 2 or 4 bit), CAD (2, 4, 8, 16 or 32 Command, Addresses and Data bits) and CTL (1 control bit). Links wider than 8 bits are built by  multiple 8-bit links in parallel to form either 16- or 32-bit links, each 8 bit group with one dedicated clock. The forwarded clock for the CTL signal is the clock for the least-significant byte. HyperTransport provides a generic message-based interrupt system, which may require an EOI indication to acknowledge the servicing of the interrupt.
Signaling 1.2-V Low-Voltage Differential Signaling (LVDS) with a 100-ohm differential impedance.
HyperTransport technology implements configuration space similarly to PCI, as defined in the PCI Local Bus Specification. This technology has the concept of I/O streams, which are groupings of traffic that can be treated independently by the HyperTransport fabric.
Control packets consist of four or eight bytes, info packets are always four bytes long and data packets contain the data payload for transactions. Data packets follow write request and read response packets. Data packets range in length from 4 to 64 bytes, in multiples of 4 bytes. The link transmitters assert CTL during control packets, and deassert it during data packets. Thus control packets can be inserted in the middle of long data packets.
In addition to the link signals, all HyperTransport technology devices require the initialization and reset pins PWROK (power and clocks are OK and stable) and RESET. Power management functions are also included in the HyperTransport specification.
HyperTransport is available on microprocessors such as the AMD Opteron, IBM PowerPC 970, and others. This gives an advantage over connections made for example through PCI-X or even PCI Express, because of fewer chip crossings and an inherently low-latency processor communications protocol. (Specification 2.0b)

I2C  Inter-IC interface
This industry standard, a type of bus designed by Philips Semiconductors in the early 1980s, is used to connect integrated circuits (ICs). I2C is a multi-master bus, which means that multiple chips can be connected to the same bus and each one can act as a master by initiating a data transfer with support for arbitration, synchronization, and programmable clock duty cycle. Master and slave interfaces support the three different speed modes, and 7 and 10-bit addresses. Each of the interfaces can be independently included in an ASIC depending on the ASICs role on the I2C bus.
I2C is used in many devices, especially video devices such as computer monitors, televisions and VCRs.

IrDA Infrared Data Association
IrDA Data is recommended for high speed short range, line of sight, point-to-point cordless data transfer - suitable for PCs and small mobile devices targeted at 4Mb/s. IrDA Control is recommended in-room cordless peripherals to hostPC. PC99 for lower speed, full cross range, point-to-point or to-multipoint cordless controller defined for 1way or 2 way communication. Since 1994," IrDA DATA" defines a standard for an interoperable universal two way cordless infrared light transmission data port. IrDA Data Protocols consist of a mandatory set of protocols and a set of optional protocols. The mandatory protocols are listed below.

  • PHY (Physical Signaling Layer)
  • IrLAP (Link Access Protocol)
  • IrLMP (Link Management Protocol and Information Access Service (IAS))

Physical IrDA Data Signaling
Range: Continuous operation from contact to at least 1 meter (typically 2 meters can be reached). A low power version relaxes the range objective for operation from contact through at least 20 cm between low power devices and 30 cm between low power and standard power devices. This implementation affords 10 times less power consumption. These parameters are termed the required maximum ranges by certain classes of IrDA featured devices and sets the end user expectation for discovery, recognition and performance.
Bi-directional communication is the basis of all specifications Data transmission from 9600 b/s with primary speed/cost steps of 115 kb/s and maximum speed up to 4 Mb/s Data packets are protected using a CRC (CRC-16 for speeds up to 1.152Mb/s and CRC-32 at 4 Mb/s).

IrDA Link Access Protocol (IrLAP)

  • Provides a device-to-device connection for the reliable, orderedtransfer of data.
  • Device discover procedures.
  • Handles hidden nodes.
  • IrDA Link Management Protocol (IrLMP)
    Provides multiplexing of the IrLAP layer
  • Multiple channels above an IrLAP connection
  • Provides protocol and service discovery via the Information Access Service (IAS)
  • Optional IrDA Data Protocols
    Tiny TP
    - provides flow control on IrLMP connections with an optional Segmentation and Reassembly service.
  • IrCOMM - provides COM (serial and parallel) port emulation for legacy COM applications, printing and modem devices
  • OBEX™ - provides object exchange services similar to HTTP.
  • IrDA Lite - provides methods of reducing the size of IrDA code while maintaining compatibility with full implementations
  • IrTran-P - provides image exchange protocol used in Digital Image capture devices/cameras
  • IrMC - specifications on how mobile telephony and communication devices can exchange information. This includes phonebook, calendar, and message data. Also how call control and real-time voice are handled  (RTCON) calendar
  • IrLAN - Describes a protocol used to support IR wireless access to local area networks

InfiniBand Architecture (IBA) is a new serial 2.5Gb high bandwidth server I/O technology specification that’s poised to revolutionize Internet data centers. An IBA system can range from a small server with one processor and a few I/O devices to a massively parallel supercomputer installation with hundreds of processors and thousands of I/O devices. IBA defines a switched communications fabric allowing many devices to concurrently communicate with high bandwidth and low latency in a protected, remotely managed environment. State-of-the-art InfiniBand switch chips provide 48 GB/s of non-blocking aggregate bandwidth over 24-ports with 200 ns latency.
IBA hardware off-loads from the CPU much of the I/O communications operation. This allows multiple concurrent communications without the traditional overhead associated with communicating protocols. IBA allows I/O units to communicate among themselves and with any or all of the processor nodes in a system. Thus a "slow" I/O unit has the same communications capability as any processor node.
InfiniBand Architecture’s simple connectivity, improved bandwidth and enhanced interoperability features simplifies and speeds server-to-server connections and links to other server-related systems such as remote storage and networking devices. IBA supports scalability required for future IO performance.

IBTA: InfiniBand Trade Association

InfiniPath directly connects to HyperTransport links.

The ISA bus mostly found in PCs consists of two connectors, one larger than the other. The larger 62-pin connector contains enough control signals, address, and data lines to support an 8-bit card. The smaller 36-pin connector adds 8 more data lines and additional IRQ and DMA control lines to support 16-bit cards.

LA-1A/B  Look-Aside Interface
The LA-1(A) interface is a de-facto standard for linking network processors (NPUs, NSEs, ...) in applications like packet forwarding, packet classification, admission control and security. It is defined has a bandwidth of about 6.4 Gbit/s per direction, which is sufficient for table lookups (IP forwarding, packet classification, etc.) at 10-Gbit/s (OC-192) packet rates. The LA-1A interface provides following features:

  • Unidirectional read and write interfaces
  • A 24-pin address bus
  • 18-pin DDR DataIn/Out transfers 32 bits data + 4 bits of even byte parity per read
  • Port Enable Signals (E[1:0] and EP[1:0])
  • 1.5-V HSTL I/O pins as defined by JEDEC (EIA/JESD8-6)

LA-1B is running at higher speeds and allows multiple lookups at 10 Gbit/s (OC-192 rates) and single lookups at 40 Gbit/s (OC-768 rates). To allow interoperability between LA-1 and LA-1B devices, LA-1B was also defined to be backwards compatible with LA-1. LA-1B is allowed to support a 1.2-V I/O (JESD8-16) in addition to the 1.5-V I/O supported by LA-1. Thus interoperability between the existing LA-1A and next generation LA-1B devices is not a requirement.

MICROWIRE/PLUS is a versatile three wire, SI (serial input), SO (serial output), and SK (serial clock), bidirectional serial synchronous communication interface where the controller is either the master providing the shift clock (SK) or a slave accepting an external shift clock.
In MICROWIRE/PLUS serial interface, the input data on the SI pin is shifted high order first into the Least Significant Bit (LSB) of the 8-bit SIOR shift register. The output data is shifted out high order first from the Most Significant Bit (MSB) of the shift register onto the SO pin. The SIOR register is clocked on the falling edge of the SK clock signal while the input data on the SI pin is shifted into the LSB of the SIOR register on the rising edge of the SK clock.

MDIO Management Data I/O
Control interface defined by the IEEE through various clauses to the Ethernet standard IEEE802.3. MDIO is a simple two-wire serial communication bus from a management device (CPU) to management-capable transceivers (multi-port Gigabit Ethernet or 10GbE XAUI transceivers) to control the device and gather status information.

MII  Media Independent Interface
An IEEE 802.3u standard for interfacing to external transceivers (MAC Interface). Can be used with a variety of physical layers for 100/10Mbps(100BASE-TX, 100BASE-T4, 10BASE-T, etc.) (see also GMII and RMII)

PCI  Peripheral Component Interconnect
A local bus standard developed by Intel Corporation. Most modern PCs include a PCI bus in addition to a more general ISA expansion bus. Many analysts believe that PCI will eventually supplant ISA entirely. PCI is also used on newer versions of the Macintosh computer. PCI is a 64-bit bus, though it is usually implemented as a 32-bit bus. It can run at clock speeds of 33 or 66 MHz, meanwhile also at 133 MHz. At 32 bits and 33 MHz, it yields a throughput rate of 133 MBps. Although it was developed by Intel, PCI is not tied to any particular family of microprocessors.
PCI local bus is a high performance, 32-bit bus with multiplexed address/data bus. It is intended for use as an interconnect mechanism between highly integrated peripherals.
Features: Processor independent; synchronous bus; 49 signals for master (47 for target without busarbitration signals) for a 32-bit bus; configuration registers for SW auto configuration; parity on data and address lines; direct silicon connection; 5V and 3.3V IOs specified; forward & backward compatibility for 33MHz and 66MHz; hidden bus arbitration

Concurrent PCI
An enhancement to the PCI bus architecture that allows PCI and ISA buses to transfer data simultaneously.

PCI-X is developed as a new local bus (chip-to-chip interface) and used as a way to upgrade the upcoming dataflow bottleneck of the old PCI bus to 66 MHz or 133 MHz. PCI-X specification also incorporates Error Checking and Correction (ECC) and is also fully backward compatible with previous PCI generations. The PCI-X local bus introduces several major enhancements to the old PCI local bus:

  • Higher clock frequencies up to 133 MHz
  • Signaling protocol changes to enable registered inputs and outputs
  • Split transactions eliminating bandwidth-wasting bus retries
  • Restricted wait-state and bus disconnection rules for deterministic data transfers
  • Improved error recovery

The PCI-X 2.0 specification defines two new versions of PCI-X add-in cards: PCI-X 266 and PCI-X 533. PCI-X 266, runs at speeds up to 266 Mega transfers per second, enabling sustainable PCI bandwidth of more than 2.1 Gigabytes/second. PCI-X 533 runs at speeds up to 533 Mega transfers per second enabling bandwidth of more than 4.2 Gigabytes/second.

PCI-Express  Peripheral Component Interconnect Express
PCI-Express is defined as serial I/O point-to-point interconnect that uses dual simplex differential signal pairs. The intent of this serial interconnect is to establish very high bandwidth communication over a few pins. It leverages the PCI programming model to preserve customer investments in PCI interface.
This way PCI bandwidth can be economically upgraded without consuming a great number of pins while preserving software backwards compatibility. PCI-Express wants to provide a

  • local bus for serial chip-to-chip interconnects
  • method to upgrade PCI slot performance at lower costs

PCI-Express utilizes recent advances in point-to-point interconnects, switch-based technology, and packetized protocols, delivering new levels of performance and features beyond those possible with PCI or PCI-X. Power management, quality of service (QoS), hot-plug/hot-swap support, data integrity, and error handling are among some of the advanced features supported by PCI Express. It maintains important PCI attributes, such as its usage model, load-store architecture, and software interfaces, thereby facilitating easy migration from PCI/PCI-X to PCI Express.
PCI-Express does not meet the needs, nor is it intended to be an external wire protocol. Since it’s a local bus, PCI-Express does not implement the I/O sharing, transport level communication, kernel bypass support, memory protection and other higher level functions. Simply stated PCI-Express supports layers 1 & 2 of the OSI model while InfiniBand supports all of layers 1 through 4 in hardware.

Following a comparison between the different PCI standards:


Signal Level [V]

Data bits

Frequency [MHz]






133 MByte/s
1.056 Gbps





266 MByte/s
2.112 Gbps





266 MByte/s
2.112 Gbps





532 MByte/s





532 MByte/s





800 MByte/s
6.4 Gbps





1.06 GByte/s
8.512 Gbps




133 DDR

2,1 GByte/s




133 QDR

4,2 GByte/s




133 QDR

4,2 GByte/s





2.112 MByte/s
16.896 Gbps
(8x2.112 Gbps)

PCI Express


2 pins/lane

2.5Gbps max

2.0 Gbps/lane
(1, 2, 4, 8, 12, 16 or 32 lanes)

PCMCIA Personal Computer Memory Card International Association
PCMCIA is an organization consisting of some 500 companies that has developed a standard for small, credit card-sized devices, called PC Cards. Originally designed for adding memory to portable computers, the PCMCIA standard has been expanded several times and is now suitable for many types of devices. There are in fact three types of PCMCIA cards. All three have the same rectangular size (85.6 by 54 millimeters), but different widths.
Type I cards can be up to 3.3 mm thick, and are used primarily for adding additional ROM or RAM to a computer. Type II cards can be up to 5.5 mm thick. These cards are often used for modem and fax modem cards. Type III cards can be up to 10.5 mm thick, which is sufficiently large for portable disk drives. As with the cards, PCMCIA slots also come in three sizes:

  • A Type I slot can hold one Type I card
  • A Type II slot can hold one Type II card or two Type I cards
  • A Type III slot can hold one Type III card or a Type I and Type II card.

In general, you can exchange PC Cards on the fly, without rebooting your computer. For example, you can slip in a fax modem card when you want to send a fax and then, when you're done, replace the fax modem card with a memory card.

PC Parallel Port
The standard LPT port was designed for a printer connection, in cooperation with printer manufacturers. Its design was kept very simple and uses a 25-pin female CANNON plug. There are eight data lines, four output lines (control), and five input lines (status). Normally, PC waits for the printer to send "I'm ready" signal (BUSY pin), sets the data lines according to a next character to be printed, sends "New character" signal (pulse on STROBE), and waits for the printer again.

POS  Packet over SONET/SDH
The transport of frame relay, point-to-point protocol, Ethernet or other frame-based protocols directly in the SONET frame without segmentation into ATM cells

    Packet-over-SONET (POS) Physical layer interface. It is the physical layer specification for local connectivity of POS devices
  • POS-PHYTM Level 2 (PL2)
    Interface between physical layer devices (such as ATM and POS) and link layer devices (such as ATM and IP forwarding devices) at up to OC-12 line rates
  • POS-PHYTM Level 3 (PL3)
    Interface defines operations between physical layer devices (such as ATM, POS and GigE framers) and link layer devices (such as ATM, IP and GigabigEthernet forwarding devices) at the OC-48 (2.488 Gbps) aggregate line rate. The PL3 interface was developed at the SATURN® Development Group in 1998. It has since been standardized at the ATM Forum (AF-PHY-0143.000) in March 2000 and at the Optical Internetworking Forum (OIF2000.008.3) in June 2000. PL3 has been widely adopted by semiconductor and equipment vendors as it provides an efficient means to connect a variety of different physical layer devices to datalink devices using a single common system bus.
  • POS-PHYTM Level 4 (PL4)
    Also known as SPI-4. This interface specification, in balloting at he Optical Internetworking Forum and the ATM Forum, provides an industry-wide standard for 10 Gbit/s multi-service system interfaces. See also
  • POS-PHYTM Level 5 (PL5)
    An industry-wide standard for 40 Gbit/s and OC-768 multi service system interfaces

See also: SPI and SFI Interfaces

The RapidIO architecture is an electronic data communications standard for interconnecting chips on a circuit board and circuit boards using a backplane. This new high-performance, packet-switched interconnect technology was designed for embedded systems, primarily for the networking and communications markets. Industry leaders in networking, communications, semiconductors, and embedded systems founded the RapidIO Trade Association to develop and support the open standard.
Designed for networking and communications equipment, enterprise storage, and other high-performance embedded markets, the RapidIO architecture addresses the demand for higher performance networking equipment for use in the Internet infrastructure. RapidIO architecture offers the bandwidth, software independence, fault tolerance, and low latency required in the networking market. The RapidIO specification defines a high-performance interconnect architecture designed for passing data and control information between microprocessors, DSPs, communications and network processors, system memory, and peripheral devices within a system. It was designed to replace current processor and peripheral bus technologies such as PCI and proprietary processor buses. The initial RapidIO specification defines physical layer technology suitable for chip-to-chip and board-to-board communications across standard printed circuit board technology at throughputs exceeding 10 Gbits per second utilizing low voltage differential signaling (LVDS) technology. Unlike other next-generation I/O technologies, RapidIO technology is transparent to application software, and does not require special device drivers. Additionally, it has no impact on operating system software. The RapidIO Interconnect can also be a bridge to other bus technologies such as PCI, PCI-X, and system area networks like InfiniBand. A rich variety of features are provided in the RapidIO interconnect including high data bandwidth capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models. Parallel as well as serial RapidIO interface versions are specified. In difference to RapidIO Infiniband was more specified for system-to-system connections.
  Features: full duplex, serial 1bit/4bit (8B10B, ) and parallel 8bit/16bit version, LVDS, 3 layer architecture, flow control, error detection, hot swapping.

Serial RapidIO
Serial RapidIO is a high-performance, low pin-count, switch fabric serial interconnect for applications such as DSP farms and newly emerging serial back plane applications. Serial RapidIO preserves the upper layer specifications, protecting previous investment in parallel RapidIO designs and verification tasks. Serial RapidIO is based on signaling technology found in Fibre Channel, 10Gbit Ethernet XAUI interfaces and Infiniband. It additionally includes a low-power transmission mode. It operates at 1.25, 2.5 and 3.125 Gbit/s, providing the required bandwidth for signal processors and back plane applications. The specification defines both a single differential link in each direction between devices and support for ganging four links together for higher throughput. On system level, designers can connect parallel and serial RapidIO devices through RapidIO switches without using special bridging functions.

RGMII  Reduced Gigabit Media Independent Interface
RGMII reduces the maximum number of GMII I/O pins from 23  to just 12 (counting the control pins). This is done by multiplexing four data signals with a control signal on both edges of the reference clock.

RMII Reduced Media Independent Interface
Specified as a low pin count interface (MAC Interface) derived from the MII (Media Independent Interface) intended for use between Ethernet PHYs and Switch or Repeater ASICs for 10Mbps and 100Mbps. Under IEEE 802.3u an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY interfaces such as Switches or port switched repeaters, the number of pins can add significant cost as the port counts increase. Typical switch products in the industry today offer 12 to 24 ports in a single device. At 6 pins per port and 1 pin per switch ASIC, the proposed RMII would save 119 pins plus the extra power and ground pins to support those additional pins for a 12 port switch ASIC.
The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u MII interface. Architecturally, the Reduced MII interface is an additional reconciliation layer on either side of the MII but can be imple-mented in the absence of an MII.

Short for recommended standard-232C, a standard interface approved by the Electronic Industries Association (EIA) for connecting serial devices. In 1987, the EIA released a new version of the standard and changed the name to EIA-232-D. And in 1991, the EIA teamed up with Telecommunications Industry association (TIA) and issued a new version of the standard called EIA/TIA-232-E. Many people, however, still refer to the standard as RS-232C, or just RS-232.
Almost all modems conform to the EIA-232 standard and most personal computers have an EIA-232 port for connecting a modem or other device. In addition to modems, many display screens, mice, and serial printers are designed to connect to a EIA-232 port. In EIA-232 parlance, the device that connects to the interface is called a Data Communications Equipment (DCE) and the device to which it connects (e.g., the computer) is called a Data Terminal Equipment (DTE).
The EIA-232 standard supports two types of connectors -- a 25-pin D-type connector (DB-25) and a 9-pin D-type connector (DB-9). The type of serial communications used by PCs requires only 9 pins so either type of connector will work equally well.
Although EIA-232 is still the most common standard for serial communication, the EIA has recently defined successors to EIA-232 called RS-422 and RS-423. The new standards are backward compatible so that RS-232 devices can connect to an RS-422 port.
Maximum data rate can now reach 120kbps at cable length of 10 to 20 meters with a max. load capacitance of 1200pF.

RS-422 and RS-423
Standard interfaces approved by the Electronic Industries Association (EIA) for connecting serial devices. The RS-422 and RS-423 standards are designed to replace the older RS-232 standard because they support higher data rates and greater immunity to electrical interference. All Apple Macintosh computers contain an RS-422 port that can also be used for RS-232C communication. RS-422 supports multipoint connections whereas RS-423 supports only point-to-point onnections. RS-422 has a max. data rate of 10Mbps, for RS-423 cable length rates between 30 (120kbps) and 1200 meters (3kbps) are possible.

An Electronics Industry Association (EIA) standard for multipoint communications. It supports several types of connectors, including DB-9 and DB-37. RS-485 is similar to RS-422 but can support more nodes per line because it uses lower-impedance drivers and receivers. Up to 32 receivers and 32 drivers can be connected to a single RS-485 bus.

SCSI Small Computer System Interface
Parallel interface standard used by PCs and many UNIX systems for attaching peripheral devices. SCSI interfaces provide for faster data transmission rates (up to 80 megabytes per second) than standard serial and parallel ports. In addition, you can attach many devices to a single SCSI port, so that SCSI is really an I/O bus rather than simply an interface.
Although SCSI is an ANSI standard, there are many variations of it, so two SCSI interfaces may be incompatible. For example, SCSI supports several types of connectors. The following varieties of SCSI are currently implemented:

  • SCSI-1: Uses an 8-bit bus, and supports data rates of 4 MBps
  • SCSI-2: Same as SCSI-1, but uses a 50-pin connector instead of a 25-pin connector, and supports multiple devices. This is what most people mean when they refer to plain SCSI.
  • Wide SCSI: Uses a wider cable (168 cable lines to 68 pins) to support 16-bit transfers.
  • Fast SCSI: Uses an 8-bit bus, but doubles the clock rate to support data rates of 10 MBps.
  • Fast Wide SCSI: Uses a 16-bit bus and supports data rates of 20 MBps.
  • Ultra SCSI: Uses an 8-bit bus, and supports data rates of 20 MBps.
  • SCSI-3: Uses a 16-bit bus and supports data rates of 40 MBps. Also called Ultra Wide SCSI.
  • Ultra2 SCSI: Uses an 8-bit bus and supports data rates of 40 MBps.
  • Wide Ultra2 SCSI: Uses a 16-bit bus and supports data rates of 80 MBps.

One of the main drawbacks of SCSI has always been bus length limitations. Originally limited to six meters, the newer standards, with their faster transfer rates and higher device populations, place even more stringent limitations on bus length. Furthermore, even at 40 MB/sec., SCSI is just not fast enough to support modern, multimedia-rich computing applications.
The eventual limitations for SCSI in terms of bus speed, reliability, cost, and device count are leading systems and storage designers to look toward serial device interfaces. Featuring data transfer rates as high as 200 MB/sec., serial interfaces rely on point-to-point interconnections, rather than busses.

SERDES devices provide a high-speed bus without a lot of connections on a backplane or cables between boxes. The applications for WarpLink SERDES transceivers are primarily where you want to eliminate interconnections yet maintain a high data throughput. The SER stands for Serializer. It takes parallel data and serializes it into a serial bit stream. The input is typically 8 parallel data, which is, encoded with an optional 8B/10B encoder. This encoding scheme converts the 8 bits data into a 10 bit format that is transmitted over a serial output "Link". The data rate on the link, in this 1 Gigabit per second data input example, is therefore 1.25 Gigabaud. The deserializer, or DES, works in reverse as it takes the serial data, decodes it and converts it back to a parallel data interface along with a "recovered" data clock.

SPI / SFI Interfaces
To promote multi-vendor interoperability at the chip-to-chip and module-to-module level, the Physical and Link Layer (PLL) Working Group within the OIF (Optical Interoperability Forum) has defined electrical interfaces at two different points within a Synchronous Optical NETwork/ Synchronous Digital Hierarchy (SONET/SDH) based communication system. These interfaces are called
  SPI  System Packet Interface   and
  SFI  SERDES Framer Interface

The SPI interface is defined on different OC levels and different phases:

  • SPI-3 OC-48 Interface
    SPI-3 was the first electrical interface defined by the OIF. It was designed to support Packet over SONET/SDH (POS) in the OC-48 (2.488 Gbps) and below environment. It defines an interface for efficient packet transfer between a physical layer (PHY) device and a link layer device. Since the SPI-3 supports data transfers at clock rates independent of the actual line bit rate, FIFOs are specified to allow the rate decoupling.
      Features: point-to-point, variable packet lenghts, 8 or 32 bits and parity at max 104MHz clock, in-band PHY port (max 256), FIFO interface
  • SPI-4 Phase 1 OC-192 Interface
    The SPI-4 Phase 1 interface is a packet and cell transfer interface that supports transfers at a nominal rate of 10 Gbps (OC-192-based) and a maximum rate of 12.8 Gbps. Transfers may be between Physical and Link layer devices, or between peer entities. SPI-4 Phase 1 is a wide and relatively low rate interface. This approach in phase 1 of the SPI-4 interfaces minimized the risk and improved the time to market of early OC-192 products. Unlike SPI-3, flow control information is passed back to the sending device on a continuous basis. The flow control information specifies whether the receiving device is full or not.
      Features: point-to-point, variable packet lenghts and fixed size cells, 64 bits (16 bits optional) and parity at 200MHz clock, HSTL, out-of-band PHY port address, FIFO interface
  • SPI-4 Phase 2 OC-192 Interface
    SPI-4 is an interface for packet and cell transfer between a Physical Layer (PHY) device and a Link Layer device. It runs at a minimum rate of 10 Gbps and supports the aggregate bandwidths required of ATM and Packet over SONET/SDH (POS) applications. SPI-4 Phase 2 specifies a higher-speed and narrower interface than defined in SPI-4 Phase 1 and its transmit and receive interfaces are completely separate and independent. This allows more flexibility in the design of higher layer devices. SPI-4 is well positioned as a versatile general-purpose interface for exchanging packets anywhere within communication systems.
      Features: point-to-point, variable packet lenghts and fixed size cells, 16 bits at 311MHz double-edge clocking, LVDS, FIFO interface
  • SFI-4 OC-192 Interface
    The SFI-4 interface supports transmit and receive data transfers at clock rates locked to the actual line bit rate. It is optimized for the pure transfer of data. There is no protocol or framing overhead. Information passed over the interface is serialized by the SERDES and transmitted on the external link.
      Features: point-to-point, 16 bits at 622MHz clock or 311,04MHz double-edge clocking (optional), LVDS, FIFO interface, up to 10.66Gbps

SDH  Synchronous Digital Hierarchy
An international standard for synchronous data transmission over fiber optic cables. The North American equivalent of SDH is SONET. SDH defines a standard rate of transmission at 155.52 Mbps, which is referred to as STS-3 at the electrical level and STM-1 for SDH.

SONET  Synchronous Optical Network
A standard for connecting fiber-optic transmission systems and was proposed by Bellcore in the middle 1980s and is now an ANSI standard. SONET defines interface standards at the physical layer of the OSI seven-layer model. The standard defines a hierarchy of interface rates that allow data streams at different rates to be multiplexed. SONET establishes Optical Carrier (OC) levels from 51.8 Mbps (about the same as a T-3 line) to 2.48 Gbps. Prior rate standards used by different countries specified rates that were not compatible for multiplexing. With the implementation of SONET, communication carriers throughout the world can interconnect their existing digital carrier and fiber optic systems.
The international equivalent of SONET, standardized by the ITU, is called SDH.

USB  Universal Serial Bus
An external bus standard that supports data transfer rates of 12 Mbps. A single USB port can be used to connect up to 127 peripheral devices, such as mice, modems, and keyboards. USB also supports Plug-and-Play installation and hot plugging. Starting in 1996, a few computer manufacturers started including USB support in their new machines. It wasn't until the release of the best-selling iMac in 1998 that USB became widespread. It is expected to completely replace serial and parallel ports.

USB On-The-Go
Many of the new peripherals now using USB are portable devices generating a growing need for them to communicate directly with each other when no PC is available. The On-The-Go Supplement addresses this need for mobile interconnectivity by allowing a USB peripheral to have the following enhancements:

  • Limited host capability to communicate with selected other USB peripherals
  • A small USB connector to fit the mobile form factor
  • Low power features to preserve battery life

UTOPIA Universal Test & Operations PHY Interface for ATM
The ATM forum defines this standard interface to allow ATM compliant physical layer devices to easily connect to other higher-level devices. This interface allows the connection to any commercially available external PHY devices on the market.
Utopia is defined by the ATM Forum to provide a standard interface between ATM devices and ATM PHY or SAR (segmentation and Re-assembly) devices. The Utopia Standard defines a full duplex bus interface with a Master/Slave paradigm. The Slave interface responds to the requests from the Master. The Master performs PHY arbitration and initiates data transfers to and from the Slave device. The ATM forum has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps (L2) to 3.2Gbit/s (L3). The following Table gives an overview of the main differences in these three levels.

Utopia Level

Interface Width

Max. Interface Speed

Maximum Throughput


8 bit


200 Mbps (typ. OC3 155 Mbps)


8/16 bit


800 Mbps (typ. OC12 622 Mbps)


8/32 bit


3.2 Gbps (typ. OC48 2.5 Gbps)

Utopia Level 1 implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16 Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the interface. In addition to the differences in throughput, Utopia Level 2 uses a shared bus offering to physically share a single interface bus between one master and up to 31 slave devices (Multi-PHY or MPHY operation). This allows the implementation of aggregation units that multiplex several slave devices to a single Master device. The Level 1 and Level 3 are point-to-point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion of multiple slaves, but they must be implemented in a single physical device connected to the Utopia Interface.
Utopia provides flow control to allow both ATM and PHY to throttle the transfer rate. There are two control methods (octet and cell) sharing the same flow control signal.

V.24, V.35, V.42, V.110, V.120, V.FAST
Interface standards that govern the attachment of data terminal equipment to data communications equipment.

VL-Bus Vesa Local Bus
Vesa Local bus offers both 32-bit and 64-bit local bus, supporting video adapter, SCSI host adapter and network adapter. The PCI bus was rapidly replacing this bus.

System-on-Chip (SoC) interface standard that gives a simple and flexible solution of IP core (intellectual property) integration on a chip (ASIC, FPGA) which are supporting this standard. WISHBONE uses a MASTER/SLAVE architecture that is similar to that of VMEbus. Cores with MASTER interfaces initiate data transfers to participating SLAVEs. They communicate with each other through a common interconnection core called the INTERCON which is specified in four types of structures:

  • Point-to-point
  • Data flow
  • Shared bus
  • Crossbar switch

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